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BurstDisassembler.Core.ARM64.info.cs 132KB

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  1. using System;
  2. using System.Linq;
  3. namespace Unity.Burst.Editor
  4. {
  5. internal partial class BurstDisassembler
  6. {
  7. internal class ARM64InstructionInfo
  8. {
  9. internal static bool GetARM64Info(string instructionName, out string instructionInfo)
  10. {
  11. var instr = ARM64AsmTokenKindProvider.TryRemoveT(new StringSlice(instructionName));
  12. var retVal = TryFindInstructionInfo(instr, out instructionInfo);
  13. if (retVal)
  14. {
  15. return retVal;
  16. }
  17. // Could not find info, so try and remove possible instruction condition code.
  18. instr = ARM64AsmTokenKindProvider.TryRemoveCond(instr);
  19. return TryFindInstructionInfo(instr, out instructionInfo);
  20. }
  21. private static bool TryFindInstructionInfo(StringSlice instr, out string instructionInfo)
  22. {
  23. var returnValue = true;
  24. switch (instr.ToString())
  25. {
  26. case "bkpt":
  27. instructionInfo = "Functions as breakpoint by causing the core to enter Debug state.";
  28. break;
  29. case "usat":
  30. instructionInfo = "Unsigned saturate to any bit position, with optional shift before saturating.";
  31. break;
  32. case "stmia":
  33. case "stm":
  34. instructionInfo = "Store multiple registers incrementing address after each transfer.";
  35. break;
  36. case "stmib":
  37. instructionInfo = "Store multiple registers incrementing address before each transfer.";
  38. break;
  39. case "stmda":
  40. instructionInfo = "Store multiple registers decrement address after each transfer.";
  41. break;
  42. case "stmdb":
  43. instructionInfo = "Store multiple registers decrement address before each transfer.";
  44. break;
  45. case "ldmia":
  46. case "ldm":
  47. instructionInfo = "Load multiple registers incrementing address after each transfer.";
  48. break;
  49. case "ldmib":
  50. instructionInfo = "Load multiple registers incrementing address before each transfer.";
  51. break;
  52. case "ldmda":
  53. instructionInfo = "Load multiple registers decrement address after each transfer.";
  54. break;
  55. case "ldmdb":
  56. instructionInfo = "Load multiple registers decrement addres before each transfer.";
  57. break;
  58. case "adc":
  59. instructionInfo = "Add with Carry.";
  60. break;
  61. case "add":
  62. case "addw":
  63. instructionInfo = "Add.";
  64. break;
  65. case "adds":
  66. instructionInfo = "Add, setting flags.";
  67. break;
  68. case "vadd":
  69. instructionInfo = "Adds corresponding elements of two vectors.";
  70. break;
  71. case "vaddl":
  72. instructionInfo = "Vector add long.";
  73. break;
  74. case "vaddw":
  75. instructionInfo = "Vector add wide.";
  76. break;
  77. case "adr":
  78. instructionInfo = "Form PC-relative address.";
  79. break;
  80. case "adrl":
  81. instructionInfo = "Loads a program or register-relative address.";
  82. break;
  83. case "adrp":
  84. instructionInfo = "Form PC-relative address to 4KB page.";
  85. break;
  86. case "and":
  87. instructionInfo = "Bitwise AND.";
  88. break;
  89. case "asr":
  90. instructionInfo = "Arithmetic Shift Right.";
  91. break;
  92. case "asrs":
  93. instructionInfo = "Arithmetic Shift Right, setting flags.";
  94. break;
  95. case "uxtab":
  96. instructionInfo = "Zero extend Byte and Add.";
  97. break;
  98. case "uxtah":
  99. instructionInfo = "Zero extend Halfword and Add. Extends a 16-bit value to a 32-bit value.";
  100. break;
  101. case "at":
  102. instructionInfo = "Address Translate.";
  103. break;
  104. case "it":
  105. case "itt":
  106. case "ittt":
  107. case "itttt":
  108. instructionInfo = "If-Then condition for the next #t instruction(s).";
  109. break;
  110. case "ite":
  111. case "itte":
  112. case "itee":
  113. case "ittee":
  114. case "ittte":
  115. instructionInfo = "If-Then-Else condition running next #t instruction(s) if true and then " +
  116. "the instruction thereafter if condition is false.";
  117. break;
  118. case "b":
  119. instructionInfo = "Branch.";
  120. break;
  121. case "bfi":
  122. instructionInfo = "Bitfield Insert.";
  123. break;
  124. case "bfm":
  125. instructionInfo = "Bitfield Move.";
  126. break;
  127. case "bfxil":
  128. instructionInfo = "Bitfield extract and insert at low end.";
  129. break;
  130. case "bic":
  131. instructionInfo = "Bitwise Bit Clear.";
  132. break;
  133. case "bl":
  134. instructionInfo = "Branch with Link.";
  135. break;
  136. case "blr":
  137. instructionInfo = "Branch with Link to Register.";
  138. break;
  139. case "br":
  140. instructionInfo = "Branch to Register.";
  141. break;
  142. case "brk":
  143. instructionInfo = "Breakpoint instruction.";
  144. break;
  145. case "cbnz":
  146. instructionInfo = "Compare and Branch on Nonzero.";
  147. break;
  148. case "cbz":
  149. instructionInfo = "Compare and Branch on Zero.";
  150. break;
  151. case "ccmn":
  152. instructionInfo = "Conditional Compare Negative.";
  153. break;
  154. case "ccmp":
  155. instructionInfo = "Conditional Compare.";
  156. break;
  157. case "clrex":
  158. instructionInfo = "Clear Exclusive.";
  159. break;
  160. case "cls":
  161. instructionInfo = "Count leading sign bits.";
  162. break;
  163. case "clz":
  164. instructionInfo = "Count leading zero bits.";
  165. break;
  166. case "cmn":
  167. instructionInfo = "Compare Negative.";
  168. break;
  169. case "cmp":
  170. instructionInfo = "Compare.";
  171. break;
  172. case "crc32b":
  173. case "crc32h":
  174. case "crc32w":
  175. case "crc32x":
  176. instructionInfo = "CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register.";
  177. break;
  178. case "crc32cb":
  179. case "crc32ch":
  180. case "crc32cw":
  181. case "crc32cx":
  182. instructionInfo = "CRC32C checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register.";
  183. break;
  184. case "csel":
  185. instructionInfo = "Conditional Select.";
  186. break;
  187. case "csinc":
  188. instructionInfo = "Conditional Select Increment.";
  189. break;
  190. case "csinv":
  191. instructionInfo = "Conditional Select Invert.";
  192. break;
  193. case "csneg":
  194. instructionInfo = "Conditional Select Negation.";
  195. break;
  196. case "dc":
  197. instructionInfo = "Data Cache operation.";
  198. break;
  199. case "dcps1":
  200. instructionInfo = "Debug Change PE State to EL1.";
  201. break;
  202. case "dcps2":
  203. instructionInfo = "Debug Change PE State to EL2.";
  204. break;
  205. case "dcps3":
  206. instructionInfo = "Debug Change PE State to EL3.";
  207. break;
  208. case "dmb":
  209. instructionInfo = "Data Memory Barrier.";
  210. break;
  211. case "drps":
  212. instructionInfo = "Debug restore process state.";
  213. break;
  214. case "dsb":
  215. instructionInfo = "Data Synchronization Barrier.";
  216. break;
  217. case "eon":
  218. instructionInfo = "Bitwise Exclusive OR NOT.";
  219. break;
  220. case "eor":
  221. instructionInfo = "Bitwise Exclusive OR.";
  222. break;
  223. case "eors":
  224. instructionInfo = "Bitwise Exclusive OR, setting flags.";
  225. break;
  226. case "eret":
  227. instructionInfo = "Returns from an exception.";
  228. break;
  229. case "extr":
  230. instructionInfo = "Extract register.";
  231. break;
  232. case "hint":
  233. instructionInfo = "Hint instruction.";
  234. break;
  235. case "hlt":
  236. instructionInfo = "Halt instruction.";
  237. break;
  238. case "hvc":
  239. instructionInfo = "Hypervisor call to allow OS code to call the Hypervisor.";
  240. break;
  241. case "ic":
  242. instructionInfo = "Instruction Cache operation.";
  243. break;
  244. case "isb":
  245. instructionInfo = "Instruction Synchronization Barrier.";
  246. break;
  247. case "lsl":
  248. instructionInfo = "Logical Shift Left.";
  249. break;
  250. case "lsls":
  251. instructionInfo = "Logical Shift Left, setting flags.";
  252. break;
  253. case "lsr":
  254. instructionInfo = "Logical Shift Right.";
  255. break;
  256. case "lsrs":
  257. instructionInfo = "Logical Shift Right, setting flags.";
  258. break;
  259. case "smmul":
  260. instructionInfo = "Signed Most significant word Multiply.";
  261. break;
  262. case "umaal":
  263. instructionInfo = "Unsigned Multiply Accumulate Accumulate Long.";
  264. break;
  265. case "madd":
  266. instructionInfo = "Multiply-Add.";
  267. break;
  268. case "mneg":
  269. instructionInfo = "Multiply-Negate.";
  270. break;
  271. case "beq":
  272. instructionInfo = "Conditional branch Equal.";
  273. break;
  274. case "bne":
  275. instructionInfo = "Conditional branch Not equal.";
  276. break;
  277. case "bcs":
  278. instructionInfo = "Conditional branch Carry set (identical to HS).";
  279. break;
  280. case "bhs":
  281. instructionInfo = "Conditional branch Unsigned higher or same (identical to CS).";
  282. break;
  283. case "bcc":
  284. instructionInfo = "Conditional branch Carry clear (identical to LO).";
  285. break;
  286. case "blo":
  287. instructionInfo = "Conditional branch Unsigned lower (identical to CC).";
  288. break;
  289. case "bmi":
  290. instructionInfo = "Conditional branch Minus or negative result.";
  291. break;
  292. case "bpl":
  293. instructionInfo = "Conditional branch Positive or zero result.";
  294. break;
  295. case "bvs":
  296. instructionInfo = "Conditional branch Overflow.";
  297. break;
  298. case "bvc":
  299. instructionInfo = "Conditional branch No overflow.";
  300. break;
  301. case "bhi":
  302. instructionInfo = "Conditional branch Unsigned higher.";
  303. break;
  304. case "bls":
  305. instructionInfo = "Conditional branch Unsigned lower or same.";
  306. break;
  307. case "bge":
  308. instructionInfo = "Conditional branch Signed greater than or equal.";
  309. break;
  310. case "blt":
  311. instructionInfo = "Conditional branch Signed less than.";
  312. break;
  313. case "bgt":
  314. instructionInfo = "Conditional branch Signed greater than.";
  315. break;
  316. case "ble":
  317. instructionInfo = "Conditional branch Signed less than or equal.";
  318. break;
  319. case "bal":
  320. instructionInfo = "Conditional branch Always (this is the default).";
  321. break;
  322. case "bnv":
  323. instructionInfo = "Conditional branch No overflow.";
  324. break;
  325. case "bx":
  326. instructionInfo = "Branch and exchange instruction set.";
  327. break;
  328. case "blx":
  329. instructionInfo =
  330. "transfers program execution to the address specified by label and stores the " +
  331. "address of the next instruction in the LR (R14) register. BLX can change the core state from ARM to Thumb, or from Thumb to ARM.";
  332. break;
  333. case "bxj":
  334. instructionInfo = "Branch and change Jazelle state. Jazelle state means the processor executes Java bytecodes.";
  335. break;
  336. case "mov":
  337. instructionInfo = "Move.";
  338. break;
  339. case "movs":
  340. instructionInfo = "Move, setting condition flags.";
  341. break;
  342. case "movl":
  343. instructionInfo = "Load a register with eiter a 32-bit or 64-bit immediate value, or any adress.";
  344. break;
  345. case "vmov":
  346. instructionInfo = "Inset a floating-point immediate value in a single-precision or double-precision register, or" +
  347. "copy one register into another register.";
  348. break;
  349. case "movk":
  350. instructionInfo = "Move wide with keep.";
  351. break;
  352. case "movn":
  353. instructionInfo = "Move wide with NOT.";
  354. break;
  355. case "movz":
  356. instructionInfo = "Move wide with zero.";
  357. break;
  358. case "movt":
  359. instructionInfo = "Move to top half of register.";
  360. break;
  361. case "movw":
  362. instructionInfo = "Move word.";
  363. break;
  364. case "mrs":
  365. instructionInfo = "Move System Register.";
  366. break;
  367. case "msr":
  368. instructionInfo = "Move immediate value to Special Register.";
  369. break;
  370. case "msub":
  371. instructionInfo = "Multiply-Subtract.";
  372. break;
  373. case "mul":
  374. instructionInfo = "Multiply.";
  375. break;
  376. case "muls":
  377. instructionInfo = "Multiply, setting flags.";
  378. break;
  379. case "vmul":
  380. instructionInfo = "Multiplies corresponding elements in two vectors, and places the results in the destination vector.";
  381. break;
  382. case "mvn":
  383. instructionInfo = "Bitwise NOT.";
  384. break;
  385. case "mvns":
  386. instructionInfo = "Bitwise NOT, setting flags.";
  387. break;
  388. case "neg":
  389. instructionInfo = "Negate.";
  390. break;
  391. case "ngc":
  392. instructionInfo = "Negate with Carry.";
  393. break;
  394. case "nop":
  395. instructionInfo = "No Operation.";
  396. break;
  397. case "orn":
  398. instructionInfo = "Bitwise OR NOT.";
  399. break;
  400. case "orr":
  401. instructionInfo = "Bitwise OR.";
  402. break;
  403. case "orrs":
  404. instructionInfo = "Bitwise OR, setting flags.";
  405. break;
  406. case "rbit":
  407. instructionInfo = "Reverse Bits.";
  408. break;
  409. case "ret":
  410. instructionInfo = "Return from subroutine.";
  411. break;
  412. case "rev16":
  413. instructionInfo = "Reverse bytes in 16-bit halfwords.";
  414. break;
  415. case "rev32":
  416. instructionInfo = "Reverse bytes in 32-bit words.";
  417. break;
  418. case "rev64":
  419. instructionInfo = "Reverse Bytes.";
  420. break;
  421. case "rev":
  422. instructionInfo = "Reverse Bytes.";
  423. break;
  424. case "rrx":
  425. instructionInfo = "Rotate right with extend.";
  426. break;
  427. case "ror":
  428. instructionInfo = "Rotate right.";
  429. break;
  430. case "sbc":
  431. instructionInfo = "Subtract with Carry.";
  432. break;
  433. case "sbfiz":
  434. instructionInfo = "Signed Bitfield Insert in Zero.";
  435. break;
  436. case "sbfm":
  437. instructionInfo = "Signed Bitfield Move.";
  438. break;
  439. case "sbfx":
  440. instructionInfo = "Signed Bitfield Extract.";
  441. break;
  442. case "sdiv":
  443. instructionInfo = "Signed Divide.";
  444. break;
  445. case "sev":
  446. instructionInfo = "Send Event.";
  447. break;
  448. case "sevl":
  449. instructionInfo = "Send Event Local.";
  450. break;
  451. case "smaddl":
  452. instructionInfo = "Signed Multiply-Add Long.";
  453. break;
  454. case "smc":
  455. instructionInfo = "Supervisor call to allow OS or Hypervisor code to call the Secure Monitor.";
  456. break;
  457. case "smnegl":
  458. instructionInfo = "Signed Multiply-Negate Long.";
  459. break;
  460. case "smsubl":
  461. instructionInfo = "Signed Multiply-Subtract Long.";
  462. break;
  463. case "smulh":
  464. instructionInfo = "Signed Multiply High.";
  465. break;
  466. case "smull":
  467. instructionInfo = "Signed Multiply Long.";
  468. break;
  469. case "sub":
  470. case "subw":
  471. instructionInfo = "Subtract.";
  472. break;
  473. case "vsub":
  474. instructionInfo = "Subtract the elements of one vector from the corresponding elements of another " +
  475. "vector, and places the results in the destination vector.";
  476. break;
  477. case "subs":
  478. instructionInfo = "Subtract (extended register), setting flags.";
  479. break;
  480. case "rsb":
  481. instructionInfo = "Reverse subtract i.e. for \"rsb {Rd, } Rn, <Operand2>\" Rn is subtracted " +
  482. "from operand2 and saved in Rd register.";
  483. break;
  484. case "rsbs":
  485. instructionInfo = "Reverse subtract, setting flags, i.e. for \"rsb {Rd, } Rn, <Operand2>\" Rn is subtracted " +
  486. "from operand2 and saved in Rd register.";
  487. break;
  488. case "svc":
  489. instructionInfo = "Supervisor call to allow application code to call the OS.";
  490. break;
  491. case "sxtb":
  492. instructionInfo = "Signed Extend Byte.";
  493. break;
  494. case "sxth":
  495. instructionInfo = "Sign Extend Halfword.";
  496. break;
  497. case "sxtw":
  498. instructionInfo = "Sign Extend Word.";
  499. break;
  500. case "sys":
  501. instructionInfo = "System instruction.";
  502. break;
  503. case "sysl":
  504. instructionInfo = "System instruction with result.";
  505. break;
  506. case "tbnz":
  507. instructionInfo = "Test bit and Branch if Nonzero.";
  508. break;
  509. case "tbz":
  510. instructionInfo = "Test bit and Branch if Zero.";
  511. break;
  512. case "tlbi":
  513. instructionInfo = "TLB Invalidate operation.";
  514. break;
  515. case "tst":
  516. instructionInfo = ", setting the condition flags and discarding the result.";
  517. break;
  518. case "ubfiz":
  519. instructionInfo = "Unsigned Bitfield Insert in Zero.";
  520. break;
  521. case "ubfm":
  522. instructionInfo = "Unsigned Bitfield Move.";
  523. break;
  524. case "ubfx":
  525. instructionInfo = "Unsigned Bitfield Extract.";
  526. break;
  527. case "udiv":
  528. instructionInfo = "Unsigned Divide.";
  529. break;
  530. case "umaddl":
  531. instructionInfo = "Unsigned Multiply-Add Long.";
  532. break;
  533. case "umnegl":
  534. instructionInfo = "Unsigned Multiply-Negate Long.";
  535. break;
  536. case "umsubl":
  537. instructionInfo = "Unsigned Multiply-Subtract Long.";
  538. break;
  539. case "umulh":
  540. instructionInfo = "Unsigned Multiply High.";
  541. break;
  542. case "umull":
  543. instructionInfo = "Unsigned Multiply Long.";
  544. break;
  545. case "uxtb":
  546. instructionInfo = "Unsigned Extend Byte.";
  547. break;
  548. case "uxth":
  549. instructionInfo = "Unsigned Extend Halfword.";
  550. break;
  551. case "wfe":
  552. instructionInfo = "Wait For Event.";
  553. break;
  554. case "wfi":
  555. instructionInfo = "Wait For Interrupt.";
  556. break;
  557. case "yield":
  558. instructionInfo = "YIELD.";
  559. break;
  560. case "ldar":
  561. instructionInfo = "Load-Acquire Register.";
  562. break;
  563. case "ldarb":
  564. instructionInfo = "Load-Acquire Register Byte.";
  565. break;
  566. case "ldarh":
  567. instructionInfo = "Load-Acquire Register Halfword.";
  568. break;
  569. case "ldaxp":
  570. instructionInfo = "Load-Acquire Exclusive Pair of Registers.";
  571. break;
  572. case "ldaxr":
  573. instructionInfo = "Load-Acquire Exclusive Register.";
  574. break;
  575. case "ldaxrb":
  576. instructionInfo = "Load-Acquire Exclusive Register Byte.";
  577. break;
  578. case "ldaxrh":
  579. instructionInfo = "Load-Acquire Exclusive Register Halfword.";
  580. break;
  581. case "ldnp":
  582. instructionInfo = "Load Pair of Registers, with non-temporal hint.";
  583. break;
  584. case "ldp":
  585. instructionInfo = "Load Pair of Registers.";
  586. break;
  587. case "ldpsw":
  588. instructionInfo = "Load Pair of Registers Signed Word.";
  589. break;
  590. case "ldr":
  591. instructionInfo = "Load Register.";
  592. break;
  593. case "ldrb":
  594. instructionInfo = "Load Register Byte.";
  595. break;
  596. case "ldrh":
  597. instructionInfo = "Load Register Halfword.";
  598. break;
  599. case "ldrd":
  600. instructionInfo = "Load Register double.";
  601. break;
  602. case "ldrsb":
  603. instructionInfo = "Load Register Signed Byte.";
  604. break;
  605. case "ldrsh":
  606. instructionInfo = "Load Register Signed Halfword.";
  607. break;
  608. case "ldrsw":
  609. instructionInfo = "Load Register Signed Word.";
  610. break;
  611. case "ldtr":
  612. instructionInfo = "Load Register.";
  613. break;
  614. case "ldtrb":
  615. instructionInfo = "Load Register Byte.";
  616. break;
  617. case "ldtrh":
  618. instructionInfo = "Load Register Halfword.";
  619. break;
  620. case "ldtrsb":
  621. instructionInfo = "Load Register Signed Byte.";
  622. break;
  623. case "ldtrsh":
  624. instructionInfo = "Load Register Signed Halfword.";
  625. break;
  626. case "ldtrsw":
  627. instructionInfo = "Load Register Signed Word.";
  628. break;
  629. case "ldur":
  630. instructionInfo = "Load Register.";
  631. break;
  632. case "ldurb":
  633. instructionInfo = "Load Register Byte.";
  634. break;
  635. case "ldurh":
  636. instructionInfo = "Load Register Halfword.";
  637. break;
  638. case "ldursb":
  639. instructionInfo = "Load Register Signed Byte.";
  640. break;
  641. case "ldursh":
  642. instructionInfo = "Load Register Signed Halfword.";
  643. break;
  644. case "ldursw":
  645. instructionInfo = "Load Register Signed Word.";
  646. break;
  647. case "ldxp":
  648. instructionInfo = "Load Exclusive Pair of Registers.";
  649. break;
  650. case "ldxr":
  651. instructionInfo = "Load Exclusive Register.";
  652. break;
  653. case "ldxrb":
  654. instructionInfo = "Load Exclusive Register Byte.";
  655. break;
  656. case "ldxrh":
  657. instructionInfo = "Load Exclusive Register Halfword.";
  658. break;
  659. case "prfm":
  660. instructionInfo = "Prefetch Memory.";
  661. break;
  662. case "prfum":
  663. instructionInfo = "Prefetch Memory.";
  664. break;
  665. case "stlr":
  666. instructionInfo = "Store-Release Register.";
  667. break;
  668. case "stlrb":
  669. instructionInfo = "Store-Release Register Byte.";
  670. break;
  671. case "stlrh":
  672. instructionInfo = "Store-Release Register Halfword.";
  673. break;
  674. case "stlxp":
  675. instructionInfo = "Store-Release Exclusive Pair of registers.";
  676. break;
  677. case "stlxr":
  678. instructionInfo = "Store-Release Exclusive Register.";
  679. break;
  680. case "stlxrb":
  681. instructionInfo = "Store-Release Exclusive Register Byte.";
  682. break;
  683. case "stlxrh":
  684. instructionInfo = "Store-Release Exclusive Register Halfword.";
  685. break;
  686. case "stnp":
  687. instructionInfo = "Store Pair of Registers, with non-temporal hint.";
  688. break;
  689. case "stp":
  690. instructionInfo = "Store Pair of Registers.";
  691. break;
  692. case "str":
  693. instructionInfo = "Store Register.";
  694. break;
  695. case "strd":
  696. instructionInfo = "Store register double.";
  697. break;
  698. case "strb":
  699. instructionInfo = "Store Register Byte.";
  700. break;
  701. case "strh":
  702. instructionInfo = "Store Register Halfword.";
  703. break;
  704. case "sttr":
  705. instructionInfo = "Store Register.";
  706. break;
  707. case "sttrb":
  708. instructionInfo = "Store Register Byte.";
  709. break;
  710. case "sttrh":
  711. instructionInfo = "Store Register Halfword.";
  712. break;
  713. case "stur":
  714. instructionInfo = "Store Register.";
  715. break;
  716. case "sturb":
  717. instructionInfo = "Store Register Byte.";
  718. break;
  719. case "sturh":
  720. instructionInfo = "Store Register Halfword.";
  721. break;
  722. case "stxp":
  723. instructionInfo = "Store Exclusive Pair of registers.";
  724. break;
  725. case "stxr":
  726. instructionInfo = "Store Exclusive Register.";
  727. break;
  728. case "stxrb":
  729. instructionInfo = "Store Exclusive Register Byte.";
  730. break;
  731. case "stxrh":
  732. instructionInfo = "Store Exclusive Register Halfword.";
  733. break;
  734. case "fabs":
  735. instructionInfo = "Floating-point Absolute value.";
  736. break;
  737. case "fadd":
  738. instructionInfo = "Floating-point Add.";
  739. break;
  740. case "fccmp":
  741. instructionInfo = "Floating-point Conditional quiet Compare.";
  742. break;
  743. case "fccmpe":
  744. instructionInfo = "Floating-point Conditional signaling Compare.";
  745. break;
  746. case "fcmp":
  747. instructionInfo = "Floating-point quiet Compare.";
  748. break;
  749. case "fcmpe":
  750. instructionInfo = "Floating-point signaling Compare.";
  751. break;
  752. case "fcsel":
  753. instructionInfo = "Floating-point Conditional Select.";
  754. break;
  755. case "fcvt":
  756. instructionInfo = "Floating-point Convert precision.";
  757. break;
  758. case "fcvtas":
  759. instructionInfo = "Floating-point Convert to Signed integer, rounding to nearest with ties to Away.";
  760. break;
  761. case "fcvtau":
  762. instructionInfo = "Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away.";
  763. break;
  764. case "fcvtms":
  765. instructionInfo = "Floating-point Convert to Signed integer, rounding toward Minus infinity.";
  766. break;
  767. case "fcvtmu":
  768. instructionInfo = "Floating-point Convert to Unsigned integer, rounding toward Minus infinity.";
  769. break;
  770. case "fcvtns":
  771. instructionInfo = "Floating-point Convert to Signed integer, rounding to nearest with ties to even.";
  772. break;
  773. case "fcvtnu":
  774. instructionInfo = "Floating-point Convert to Unsigned integer, rounding to nearest with ties to even.";
  775. break;
  776. case "fcvtps":
  777. instructionInfo = "Floating-point Convert to Signed integer, rounding toward Plus infinity.";
  778. break;
  779. case "fcvtpu":
  780. instructionInfo = "Floating-point Convert to Unsigned integer, rounding toward Plus infinity.";
  781. break;
  782. case "fcvtzs":
  783. instructionInfo = "Floating-point Convert to Signed fixed-point, rounding toward Zero.";
  784. break;
  785. case "fcvtzu":
  786. instructionInfo = "Floating-point Convert to Unsigned fixed-point, rounding toward Zero.";
  787. break;
  788. case "fdiv":
  789. instructionInfo = "Floating-point Divide.";
  790. break;
  791. case "fmadd":
  792. instructionInfo = "Floating-point fused Multiply-Add.";
  793. break;
  794. case "fmax":
  795. instructionInfo = "Floating-point Maximum.";
  796. break;
  797. case "fmaxnm":
  798. instructionInfo = "Floating-point Maximum Number.";
  799. break;
  800. case "fmin":
  801. instructionInfo = "Floating-point Minimum.";
  802. break;
  803. case "fminnm":
  804. instructionInfo = "Floating-point Minimum Number.";
  805. break;
  806. case "fmov":
  807. instructionInfo = "Floating-point Move register without conversion.";
  808. break;
  809. case "fmsub":
  810. instructionInfo = "Floating-point Fused Multiply-Subtract.";
  811. break;
  812. case "fmul":
  813. instructionInfo = "Floating-point Multiply.";
  814. break;
  815. case "fneg":
  816. instructionInfo = "Floating-point Negate.";
  817. break;
  818. case "fnmadd":
  819. instructionInfo = "Floating-point Negated fused Multiply-Add.";
  820. break;
  821. case "fnmsub":
  822. instructionInfo = "Floating-point Negated fused Multiply-Subtract.";
  823. break;
  824. case "fnmul":
  825. instructionInfo = "Floating-point Multiply-Negate.";
  826. break;
  827. case "frinta":
  828. instructionInfo = "Floating-point Round to Integral, to nearest with ties to Away.";
  829. break;
  830. case "frinti":
  831. instructionInfo = "Floating-point Round to Integral, using current rounding mode.";
  832. break;
  833. case "frintm":
  834. instructionInfo = "Floating-point Round to Integral, toward Minus infinity.";
  835. break;
  836. case "frintn":
  837. instructionInfo = "Floating-point Round to Integral, to nearest with ties to even.";
  838. break;
  839. case "frintp":
  840. instructionInfo = "Floating-point Round to Integral, toward Plus infinity.";
  841. break;
  842. case "frintx":
  843. instructionInfo = "Floating-point Round to Integral exact, using current rounding mode.";
  844. break;
  845. case "frintz":
  846. instructionInfo = "Floating-point Round to Integral, toward Zero.";
  847. break;
  848. case "fsqrt":
  849. instructionInfo = "Floating-point Square Root.";
  850. break;
  851. case "fsub":
  852. instructionInfo = "Floating-point Subtract.";
  853. break;
  854. case "scvtf":
  855. instructionInfo = "Signed fixed-point Convert to Floating-point.";
  856. break;
  857. case "ucvtf":
  858. instructionInfo = "Unsigned fixed-point Convert to Floating-point.";
  859. break;
  860. case "abs":
  861. instructionInfo = "Absolute value.";
  862. break;
  863. case "vabs":
  864. instructionInfo = "Returns the absolute value of each element in a vector.";
  865. break;
  866. case "addp":
  867. instructionInfo = "Add Pair of elements.";
  868. break;
  869. case "cmeq":
  870. instructionInfo = "Compare bitwise Equal.";
  871. break;
  872. case "cmge":
  873. instructionInfo = "Compare signed Greater than or Equal.";
  874. break;
  875. case "cmgt":
  876. instructionInfo = "Compare signed Greater than.";
  877. break;
  878. case "cmhi":
  879. instructionInfo = "Compare unsigned Higher.";
  880. break;
  881. case "cmhs":
  882. instructionInfo = "Compare unsigned Higher or Same.";
  883. break;
  884. case "cmle":
  885. instructionInfo = "Compare signed Less than or Equal to zero.";
  886. break;
  887. case "cmlt":
  888. instructionInfo = "Compare signed Less than zero.";
  889. break;
  890. case "cmtst":
  891. instructionInfo = "Compare bitwise Test bits nonzero.";
  892. break;
  893. case "dup":
  894. instructionInfo = "Duplicate vector element to scalar.";
  895. break;
  896. case "fabd":
  897. instructionInfo = "Floating-point Absolute Difference.";
  898. break;
  899. case "facge":
  900. instructionInfo = "Floating-point Absolute Compare Greater than or Equal.";
  901. break;
  902. case "facgt":
  903. instructionInfo = "Floating-point Absolute Compare Greater than.";
  904. break;
  905. case "faddp":
  906. instructionInfo = "Floating-point Add Pair of elements.";
  907. break;
  908. case "fcmeq":
  909. instructionInfo = "Floating-point Compare Equal.";
  910. break;
  911. case "fcmge":
  912. instructionInfo = "Floating-point Compare Greater than or Equal.";
  913. break;
  914. case "fcmgt":
  915. instructionInfo = "Floating-point Compare Greater than.";
  916. break;
  917. case "fcmle":
  918. instructionInfo = "Floating-point Compare Less than or Equal to zero.";
  919. break;
  920. case "fcmlt":
  921. instructionInfo = "Floating-point Compare Less than zero.";
  922. break;
  923. case "fcvtxn":
  924. instructionInfo = "Floating-point Convert to lower precision Narrow, rounding to odd.";
  925. break;
  926. case "fmaxnmp":
  927. instructionInfo = "Floating-point Maximum Number of Pair of elements.";
  928. break;
  929. case "fmaxp":
  930. instructionInfo = "Floating-point Maximum of Pair of elements.";
  931. break;
  932. case "fminnmp":
  933. instructionInfo = "Floating-point Minimum Number of Pair of elements.";
  934. break;
  935. case "fminp":
  936. instructionInfo = "Floating-point Minimum of Pair of elements.";
  937. break;
  938. case "fmla":
  939. instructionInfo = "Floating-point fused Multiply-Add to accumulator.";
  940. break;
  941. case "fmls":
  942. instructionInfo = "Floating-point fused Multiply-Subtract from accumulator.";
  943. break;
  944. case "fmulx":
  945. instructionInfo = "Floating-point Multiply extended.";
  946. break;
  947. case "frecpe":
  948. instructionInfo = "Floating-point Reciprocal Estimate.";
  949. break;
  950. case "frecps":
  951. instructionInfo = "Floating-point Reciprocal Step.";
  952. break;
  953. case "frsqrte":
  954. instructionInfo = "Floating-point Reciprocal Square Root Estimate.";
  955. break;
  956. case "frsqrts":
  957. instructionInfo = "Floating-point Reciprocal Square Root Step.";
  958. break;
  959. case "shl":
  960. instructionInfo = "Shift Left.";
  961. break;
  962. case "sli":
  963. instructionInfo = "Shift Left and Insert.";
  964. break;
  965. case "sqabs":
  966. instructionInfo = "Signed saturating Absolute value.";
  967. break;
  968. case "sqadd":
  969. instructionInfo = "Signed saturating Add.";
  970. break;
  971. case "sqdmlal":
  972. instructionInfo = "Signed saturating Doubling Multiply-Add Long.";
  973. break;
  974. case "sqdmlsl":
  975. instructionInfo = "Signed saturating Doubling Multiply-Subtract Long.";
  976. break;
  977. case "sqdmulh":
  978. instructionInfo = "Signed saturating Doubling Multiply returning High half.";
  979. break;
  980. case "sqdmull":
  981. instructionInfo = "Signed saturating Doubling Multiply Long.";
  982. break;
  983. case "sqneg":
  984. instructionInfo = "Signed saturating Negate.";
  985. break;
  986. case "sqrdmulh":
  987. instructionInfo = "Signed saturating Rounding Doubling Multiply returning High half.";
  988. break;
  989. case "sqrshl":
  990. instructionInfo = "Signed saturating Rounding Shift Left.";
  991. break;
  992. case "sqrshrn":
  993. instructionInfo = "Signed saturating Rounded Shift Right Narrow.";
  994. break;
  995. case "sqrshrun":
  996. instructionInfo = "Signed saturating Rounded Shift Right Unsigned Narrow.";
  997. break;
  998. case "sqshl":
  999. instructionInfo = "Signed saturating Shift Left.";
  1000. break;
  1001. case "sqshlu":
  1002. instructionInfo = "Signed saturating Shift Left Unsigned.";
  1003. break;
  1004. case "sqshrn":
  1005. instructionInfo = "Signed saturating Shift Right Narrow.";
  1006. break;
  1007. case "sqshrun":
  1008. instructionInfo = "Signed saturating Shift Right Unsigned Narrow.";
  1009. break;
  1010. case "sqsub":
  1011. instructionInfo = "Signed saturating Subtract.";
  1012. break;
  1013. case "sqxtn":
  1014. instructionInfo = "Signed saturating extract Narrow.";
  1015. break;
  1016. case "sqxtun":
  1017. instructionInfo = "Signed saturating extract Unsigned Narrow.";
  1018. break;
  1019. case "sri":
  1020. instructionInfo = "Shift Right and Insert.";
  1021. break;
  1022. case "srshl":
  1023. instructionInfo = "Signed Rounding Shift Left.";
  1024. break;
  1025. case "srshr":
  1026. instructionInfo = "Signed Rounding Shift Right.";
  1027. break;
  1028. case "srsra":
  1029. instructionInfo = "Signed Rounding Shift Right and Accumulate.";
  1030. break;
  1031. case "sshl":
  1032. instructionInfo = "Signed Shift Left.";
  1033. break;
  1034. case "sshr":
  1035. instructionInfo = "Signed Shift Right.";
  1036. break;
  1037. case "ssra":
  1038. instructionInfo = "Signed Shift Right and Accumulate.";
  1039. break;
  1040. case "suqadd":
  1041. instructionInfo = "Signed saturating Accumulate of Unsigned value.";
  1042. break;
  1043. case "uqadd":
  1044. instructionInfo = "Unsigned saturating Add.";
  1045. break;
  1046. case "uqrshl":
  1047. instructionInfo = "Unsigned saturating Rounding Shift Left.";
  1048. break;
  1049. case "uqrshrn":
  1050. instructionInfo = "Unsigned saturating Rounded Shift Right Narrow.";
  1051. break;
  1052. case "uqshl":
  1053. instructionInfo = "Unsigned saturating Shift Left.";
  1054. break;
  1055. case "uqshrn":
  1056. instructionInfo = "Unsigned saturating Shift Right Narrow.";
  1057. break;
  1058. case "uqsub":
  1059. instructionInfo = "Unsigned saturating Subtract.";
  1060. break;
  1061. case "uqxtn":
  1062. instructionInfo = "Unsigned saturating extract Narrow.";
  1063. break;
  1064. case "urshl":
  1065. instructionInfo = "Unsigned Rounding Shift Left.";
  1066. break;
  1067. case "urshr":
  1068. instructionInfo = "Unsigned Rounding Shift Right.";
  1069. break;
  1070. case "ursra":
  1071. instructionInfo = "Unsigned Rounding Shift Right and Accumulate.";
  1072. break;
  1073. case "ushl":
  1074. instructionInfo = "Unsigned Shift Left.";
  1075. break;
  1076. case "ushr":
  1077. instructionInfo = "Unsigned Shift Right.";
  1078. break;
  1079. case "usqadd":
  1080. instructionInfo = "Unsigned saturating Accumulate of Signed value.";
  1081. break;
  1082. case "usra":
  1083. instructionInfo = "Unsigned Shift Right and Accumulate.";
  1084. break;
  1085. case "addhn":
  1086. case "addhn2":
  1087. instructionInfo = "Add returning High Narrow.";
  1088. break;
  1089. case "addv":
  1090. instructionInfo = "Add across Vector.";
  1091. break;
  1092. case "bif":
  1093. instructionInfo = "Bitwise Insert if False.";
  1094. break;
  1095. case "bit":
  1096. instructionInfo = "Bitwise Insert if True.";
  1097. break;
  1098. case "bsl":
  1099. instructionInfo = "Bitwise Select.";
  1100. break;
  1101. case "cnt":
  1102. instructionInfo = "Population Count per byte.";
  1103. break;
  1104. case "ext":
  1105. instructionInfo = "Extract vector from pair of vectors.";
  1106. break;
  1107. case "fcvtl":
  1108. case "fcvtl2":
  1109. instructionInfo = "Floating-point Convert to higher precision Long.";
  1110. break;
  1111. case "fcvtn":
  1112. case "fcvtn2":
  1113. instructionInfo = "Floating-point Convert to lower precision Narrow.";
  1114. break;
  1115. case "fcvtxn2":
  1116. instructionInfo = "Floating-point Convert to lower precision Narrow, rounding to odd.";
  1117. break;
  1118. case "fmaxnmv":
  1119. instructionInfo = "Floating-point Maximum Number across Vector.";
  1120. break;
  1121. case "fmaxv":
  1122. instructionInfo = "Floating-point Maximum across Vector.";
  1123. break;
  1124. case "fminnmv":
  1125. instructionInfo = "Floating-point Minimum Number across Vector.";
  1126. break;
  1127. case "fminv":
  1128. instructionInfo = "Floating-point Minimum across Vector.";
  1129. break;
  1130. case "frecpx":
  1131. instructionInfo = "Floating-point Reciprocal exponent.";
  1132. break;
  1133. case "ins":
  1134. instructionInfo = "Insert vector element from another vector element.";
  1135. break;
  1136. case "ld1":
  1137. instructionInfo = "Load multiple single-element structures to one, two, three, or four registers.";
  1138. break;
  1139. case "ld1r":
  1140. instructionInfo = "Load one single-element structure and Replicate to all lanes.";
  1141. break;
  1142. case "ld2":
  1143. instructionInfo = "Load multiple 2-element structures to two registers.";
  1144. break;
  1145. case "ld2r":
  1146. instructionInfo = "Load single 2-element structure and Replicate to all lanes of two registers.";
  1147. break;
  1148. case "ld3":
  1149. instructionInfo = "Load multiple 3-element structures to three registers.";
  1150. break;
  1151. case "ld3r":
  1152. instructionInfo = "Load single 3-element structure and Replicate to all lanes of three registers.";
  1153. break;
  1154. case "ld4":
  1155. instructionInfo = "Load multiple 4-element structures to four registers.";
  1156. break;
  1157. case "ld4r":
  1158. instructionInfo = "Load single 4-element structure and Replicate to all lanes of four registers.";
  1159. break;
  1160. case "mla":
  1161. instructionInfo = "Multiply-Add to accumulator (vector, by element).";
  1162. break;
  1163. case "mls":
  1164. instructionInfo = "Multiply-Subtract from accumulator (vector, by element).";
  1165. break;
  1166. case "movi":
  1167. instructionInfo = "Move Immediate.";
  1168. break;
  1169. case "mvni":
  1170. instructionInfo = "Move inverted Immediate.";
  1171. break;
  1172. case "not":
  1173. instructionInfo = "Bitwise NOT.";
  1174. break;
  1175. case "pmul":
  1176. instructionInfo = "Polynomial Multiply.";
  1177. break;
  1178. case "pmull":
  1179. case "pmull2":
  1180. instructionInfo = "Polynomial Multiply Long.";
  1181. break;
  1182. case "raddhn":
  1183. case "raddhn2":
  1184. instructionInfo = "Rounding Add returning High Narrow.";
  1185. break;
  1186. case "rshrn":
  1187. case "rshrn2":
  1188. instructionInfo = "Rounding Shift Right Narrow.";
  1189. break;
  1190. case "rsubhn":
  1191. case "rsubhn2":
  1192. instructionInfo = "Rounding Subtract returning High Narrow.";
  1193. break;
  1194. case "saba":
  1195. instructionInfo = "Signed Absolute difference and Accumulate.";
  1196. break;
  1197. case "sabal":
  1198. case "sabal2":
  1199. instructionInfo = "Signed Absolute difference and Accumulate Long.";
  1200. break;
  1201. case "sabd":
  1202. instructionInfo = "Signed Absolute Difference.";
  1203. break;
  1204. case "sabdl":
  1205. case "sabdl2":
  1206. instructionInfo = "Signed Absolute Difference Long.";
  1207. break;
  1208. case "sadalp":
  1209. instructionInfo = "Signed Add and Accumulate Long Pairwise.";
  1210. break;
  1211. case "saddl":
  1212. case "saddl2":
  1213. instructionInfo = "Signed Add Long.";
  1214. break;
  1215. case "saddlp":
  1216. instructionInfo = "Signed Add Long Pairwise.";
  1217. break;
  1218. case "saddlv":
  1219. instructionInfo = "Signed Add Long across Vector.";
  1220. break;
  1221. case "saddw":
  1222. case "saddw2":
  1223. instructionInfo = "Signed Add Wide.";
  1224. break;
  1225. case "shadd":
  1226. instructionInfo = "Signed Halving Add.";
  1227. break;
  1228. case "shll":
  1229. case "shll2":
  1230. instructionInfo = "Shift Left Long.";
  1231. break;
  1232. case "shrn":
  1233. case "shrn2":
  1234. instructionInfo = "Shift Right Narrow.";
  1235. break;
  1236. case "shsub":
  1237. instructionInfo = "Signed Halving Subtract.";
  1238. break;
  1239. case "smax":
  1240. instructionInfo = "Signed Maximum.";
  1241. break;
  1242. case "smaxp":
  1243. instructionInfo = "Signed Maximum Pairwise.";
  1244. break;
  1245. case "smaxv":
  1246. instructionInfo = "Signed Maximum across Vector.";
  1247. break;
  1248. case "smin":
  1249. instructionInfo = "Signed Minimum.";
  1250. break;
  1251. case "sminp":
  1252. instructionInfo = "Signed Minimum Pairwise.";
  1253. break;
  1254. case "sminv":
  1255. instructionInfo = "Signed Minimum across Vector.";
  1256. break;
  1257. case "smlabb":
  1258. case "smlabt":
  1259. case "smlatb":
  1260. case "smlatt":
  1261. instructionInfo = "Signed Multiply Accumulate performs a signed multiply accumulate operation.";
  1262. break;
  1263. case "smlal":
  1264. case "smlal2":
  1265. instructionInfo = "Signed Multiply-Add Long (vector, by element).";
  1266. break;
  1267. case "smlsl":
  1268. case "smlsl2":
  1269. instructionInfo = "Signed Multiply-Subtract Long (vector, by element).";
  1270. break;
  1271. case "smov":
  1272. instructionInfo = "Signed Move vector element to general-purpose register.";
  1273. break;
  1274. case "smull2":
  1275. instructionInfo = "Signed Multiply Long (vector, by element).";
  1276. break;
  1277. case "sqdmlal2":
  1278. instructionInfo = "Signed saturating Doubling Multiply-Add Long.";
  1279. break;
  1280. case "sqdmlsl2":
  1281. instructionInfo = "Signed saturating Doubling Multiply-Subtract Long.";
  1282. break;
  1283. case "sqdmull2":
  1284. instructionInfo = "Signed saturating Doubling Multiply Long.";
  1285. break;
  1286. case "sqrshrn2":
  1287. instructionInfo = "Signed saturating Rounded Shift Right Narrow.";
  1288. break;
  1289. case "sqrshrun2":
  1290. instructionInfo = "Signed saturating Rounded Shift Right Unsigned Narrow.";
  1291. break;
  1292. case "sqshrn2":
  1293. instructionInfo = "Signed saturating Shift Right Narrow.";
  1294. break;
  1295. case "sqshrun2":
  1296. instructionInfo = "Signed saturating Shift Right Unsigned Narrow.";
  1297. break;
  1298. case "sqxtn2":
  1299. instructionInfo = "Signed saturating extract Narrow.";
  1300. break;
  1301. case "sqxtun2":
  1302. instructionInfo = "Signed saturating extract Unsigned Narrow.";
  1303. break;
  1304. case "srhadd":
  1305. instructionInfo = "Signed Rounding Halving Add.";
  1306. break;
  1307. case "sshll":
  1308. case "sshll2":
  1309. instructionInfo = "Signed Shift Left Long.";
  1310. break;
  1311. case "ssubl":
  1312. case "ssubl2":
  1313. instructionInfo = "Signed Subtract Long.";
  1314. break;
  1315. case "ssubw":
  1316. case "ssubw2":
  1317. instructionInfo = "Signed Subtract Wide.";
  1318. break;
  1319. case "st1":
  1320. instructionInfo = "Store multiple single-element structures from one, two, three, or four registers.";
  1321. break;
  1322. case "st2":
  1323. instructionInfo = "Store multiple 2-element structures from two registers.";
  1324. break;
  1325. case "st3":
  1326. instructionInfo = "Store multiple 3-element structures from three registers.";
  1327. break;
  1328. case "st4":
  1329. instructionInfo = "Store multiple 4-element structures from four registers.";
  1330. break;
  1331. case "subhn":
  1332. case "subhn2":
  1333. instructionInfo = "Subtract returning High Narrow.";
  1334. break;
  1335. case "tbl":
  1336. instructionInfo = "Table vector Lookup.";
  1337. break;
  1338. case "tbx":
  1339. instructionInfo = "Table vector lookup extension.";
  1340. break;
  1341. case "tbb":
  1342. instructionInfo = "PC-relative forward branch using table of single byte offsets.";
  1343. break;
  1344. case "tbh":
  1345. instructionInfo = "PC-relative forward branch using table of halfword offsets.";
  1346. break;
  1347. case "trn1":
  1348. instructionInfo = "Transpose vectors.";
  1349. break;
  1350. case "trn2":
  1351. instructionInfo = "Transpose vectors.";
  1352. break;
  1353. case "uaba":
  1354. instructionInfo = "Unsigned Absolute difference and Accumulate.";
  1355. break;
  1356. case "uabal":
  1357. case "uabal2":
  1358. instructionInfo = "Unsigned Absolute difference and Accumulate Long.";
  1359. break;
  1360. case "uabd":
  1361. instructionInfo = "Unsigned Absolute Difference.";
  1362. break;
  1363. case "uabdl":
  1364. case "uabdl2":
  1365. instructionInfo = "Unsigned Absolute Difference Long.";
  1366. break;
  1367. case "uadalp":
  1368. instructionInfo = "Unsigned Add and Accumulate Long Pairwise.";
  1369. break;
  1370. case "uaddl":
  1371. case "uaddl2":
  1372. instructionInfo = "Unsigned Add Long.";
  1373. break;
  1374. case "uaddlp":
  1375. instructionInfo = "Unsigned Add Long Pairwise.";
  1376. break;
  1377. case "uaddlv":
  1378. instructionInfo = "Unsigned sum Long across Vector.";
  1379. break;
  1380. case "uaddw":
  1381. case "uaddw2":
  1382. instructionInfo = "Unsigned Add Wide.";
  1383. break;
  1384. case "uhadd":
  1385. instructionInfo = "Unsigned Halving Add.";
  1386. break;
  1387. case "uhsub":
  1388. instructionInfo = "Unsigned Halving Subtract.";
  1389. break;
  1390. case "umax":
  1391. instructionInfo = "Unsigned Maximum.";
  1392. break;
  1393. case "umaxp":
  1394. instructionInfo = "Unsigned Maximum Pairwise.";
  1395. break;
  1396. case "umaxv":
  1397. instructionInfo = "Unsigned Maximum across Vector.";
  1398. break;
  1399. case "umin":
  1400. instructionInfo = "Unsigned Minimum.";
  1401. break;
  1402. case "uminp":
  1403. instructionInfo = "Unsigned Minimum Pairwise.";
  1404. break;
  1405. case "uminv":
  1406. instructionInfo = "Unsigned Minimum across Vector.";
  1407. break;
  1408. case "umlal":
  1409. case "umlal2":
  1410. instructionInfo = "Unsigned Multiply-Add Long (vector, by element).";
  1411. break;
  1412. case "umlsl":
  1413. case "umlsl2":
  1414. instructionInfo = "Unsigned Multiply-Subtract Long (vector, by element).";
  1415. break;
  1416. case "umov":
  1417. instructionInfo = "Unsigned Move vector element to general-purpose register.";
  1418. break;
  1419. case "umull2":
  1420. instructionInfo = "Unsigned Multiply Long (vector, by element).";
  1421. break;
  1422. case "uqrshrn2":
  1423. instructionInfo = "Unsigned saturating Rounded Shift Right Narrow.";
  1424. break;
  1425. case "uqshrn2":
  1426. instructionInfo = "Unsigned saturating Shift Right Narrow.";
  1427. break;
  1428. case "uqxtn2":
  1429. instructionInfo = "Unsigned saturating extract Narrow.";
  1430. break;
  1431. case "urecpe":
  1432. instructionInfo = "Unsigned Reciprocal Estimate.";
  1433. break;
  1434. case "urhadd":
  1435. instructionInfo = "Unsigned Rounding Halving Add.";
  1436. break;
  1437. case "ursqrte":
  1438. instructionInfo = "Unsigned Reciprocal Square Root Estimate.";
  1439. break;
  1440. case "ushll":
  1441. case "ushll2":
  1442. instructionInfo = "Unsigned Shift Left Long.";
  1443. break;
  1444. case "usubl":
  1445. case "usubl2":
  1446. instructionInfo = "Unsigned Subtract Long.";
  1447. break;
  1448. case "usubw":
  1449. case "usubw2":
  1450. instructionInfo = "Unsigned Subtract Wide.";
  1451. break;
  1452. case "uzp1":
  1453. instructionInfo = "Unzip vectors.";
  1454. break;
  1455. case "uzp2":
  1456. instructionInfo = "Unzip vectors.";
  1457. break;
  1458. case "xtn":
  1459. case "xtn2":
  1460. instructionInfo = "Extract Narrow.";
  1461. break;
  1462. case "zip1":
  1463. instructionInfo = "Zip vectors.";
  1464. break;
  1465. case "zip2":
  1466. instructionInfo = "Zip vectors.";
  1467. break;
  1468. case "aesd":
  1469. instructionInfo = "AES single round decryption.";
  1470. break;
  1471. case "aese":
  1472. instructionInfo = "AES single round encryption.";
  1473. break;
  1474. case "aesimc":
  1475. instructionInfo = "AES inverse mix columns.";
  1476. break;
  1477. case "aesmc":
  1478. instructionInfo = "AES mix columns.";
  1479. break;
  1480. case "sha1c":
  1481. instructionInfo = "SHA1 hash update.";
  1482. break;
  1483. case "sha1h":
  1484. instructionInfo = "SHA1 fixed rotate.";
  1485. break;
  1486. case "sha1m":
  1487. instructionInfo = "SHA1 hash update.";
  1488. break;
  1489. case "sha1p":
  1490. instructionInfo = "SHA1 hash update.";
  1491. break;
  1492. case "sha1su0":
  1493. instructionInfo = "SHA1 schedule update 0.";
  1494. break;
  1495. case "sha1su1":
  1496. instructionInfo = "SHA1 schedule update 1.";
  1497. break;
  1498. case "sha256h2":
  1499. instructionInfo = "SHA256 hash update.";
  1500. break;
  1501. case "sha256h":
  1502. instructionInfo = "SHA256 hash update.";
  1503. break;
  1504. case "sha256su0":
  1505. instructionInfo = "SHA256 schedule update 0.";
  1506. break;
  1507. case "sha256su1":
  1508. instructionInfo = "SHA256 schedule update 1.";
  1509. break;
  1510. case "adcs":
  1511. instructionInfo = "Add with Carry, setting flags.";
  1512. break;
  1513. case "addg":
  1514. instructionInfo = "Add with Tag.";
  1515. break;
  1516. case "ands":
  1517. instructionInfo = "Bitwise AND (immediate), setting flags.";
  1518. break;
  1519. case "asrv":
  1520. instructionInfo = "Arithmetic Shift Right Variable.";
  1521. break;
  1522. case "autda":
  1523. instructionInfo = "Authenticate Data address, using key A.";
  1524. break;
  1525. case "autdza":
  1526. instructionInfo = "Authenticate Data address, using key A.";
  1527. break;
  1528. case "autdb":
  1529. instructionInfo = "Authenticate Data address, using key B.";
  1530. break;
  1531. case "autdzb":
  1532. instructionInfo = "Authenticate Data address, using key B.";
  1533. break;
  1534. case "autia":
  1535. instructionInfo = "Authenticate Instruction address, using key A.";
  1536. break;
  1537. case "autiza":
  1538. instructionInfo = "Authenticate Instruction address, using key A.";
  1539. break;
  1540. case "autia1716":
  1541. instructionInfo = "Authenticate Instruction address, using key A.";
  1542. break;
  1543. case "autiasp":
  1544. instructionInfo = "Authenticate Instruction address, using key A.";
  1545. break;
  1546. case "autiaz":
  1547. instructionInfo = "Authenticate Instruction address, using key A.";
  1548. break;
  1549. case "autib":
  1550. instructionInfo = "Authenticate Instruction address, using key B.";
  1551. break;
  1552. case "autizb":
  1553. instructionInfo = "Authenticate Instruction address, using key B.";
  1554. break;
  1555. case "autib1716":
  1556. instructionInfo = "Authenticate Instruction address, using key B.";
  1557. break;
  1558. case "autibsp":
  1559. instructionInfo = "Authenticate Instruction address, using key B.";
  1560. break;
  1561. case "autibz":
  1562. instructionInfo = "Authenticate Instruction address, using key B.";
  1563. break;
  1564. case "axflag":
  1565. instructionInfo = "Convert floating-point condition flags from Arm to external format.";
  1566. break;
  1567. case "b.cond":
  1568. instructionInfo = "Branch conditionally.";
  1569. break;
  1570. case "bfc":
  1571. instructionInfo = "Bitfield Clear, leaving other bits unchanged.";
  1572. break;
  1573. case "bics":
  1574. instructionInfo = "Bitwise Bit Clear (shifted register), setting flags.";
  1575. break;
  1576. case "blraa":
  1577. instructionInfo = "Branch with Link to Register, with pointer authentication.";
  1578. break;
  1579. case "blraaz":
  1580. instructionInfo = "Branch with Link to Register, with pointer authentication.";
  1581. break;
  1582. case "blrab":
  1583. instructionInfo = "Branch with Link to Register, with pointer authentication.";
  1584. break;
  1585. case "blrabz":
  1586. instructionInfo = "Branch with Link to Register, with pointer authentication.";
  1587. break;
  1588. case "braa":
  1589. instructionInfo = "Branch to Register, with pointer authentication.";
  1590. break;
  1591. case "braaz":
  1592. instructionInfo = "Branch to Register, with pointer authentication.";
  1593. break;
  1594. case "brab":
  1595. instructionInfo = "Branch to Register, with pointer authentication.";
  1596. break;
  1597. case "brabz":
  1598. instructionInfo = "Branch to Register, with pointer authentication.";
  1599. break;
  1600. case "bti":
  1601. instructionInfo = "Branch Target Identification.";
  1602. break;
  1603. case "cinc":
  1604. instructionInfo = "Conditional Increment.";
  1605. break;
  1606. case "cinv":
  1607. instructionInfo = "Conditional Invert.";
  1608. break;
  1609. case "cmpp":
  1610. instructionInfo = "Compare with Tag.";
  1611. break;
  1612. case "cneg":
  1613. instructionInfo = "Conditional Negate.";
  1614. break;
  1615. case "csdb":
  1616. instructionInfo = "Consumption of Speculative Data Barrier.";
  1617. break;
  1618. case "cset":
  1619. instructionInfo = "Conditional Set.";
  1620. break;
  1621. case "csetm":
  1622. instructionInfo = "Conditional Set Mask.";
  1623. break;
  1624. case "eretaa":
  1625. instructionInfo = "Exception Return, with pointer authentication.";
  1626. break;
  1627. case "eretab":
  1628. instructionInfo = "Exception Return, with pointer authentication.";
  1629. break;
  1630. case "esb":
  1631. instructionInfo = "Error Synchronization Barrier.";
  1632. break;
  1633. case "irg":
  1634. instructionInfo = "Insert Random Tag.";
  1635. break;
  1636. case "ldg":
  1637. instructionInfo = "Load Allocation Tag.";
  1638. break;
  1639. case "ldgv":
  1640. instructionInfo = "Load Allocation Tag.";
  1641. break;
  1642. case "lslv":
  1643. instructionInfo = "Logical Shift Left Variable.";
  1644. break;
  1645. case "lsrv":
  1646. instructionInfo = "Logical Shift Right Variable.";
  1647. break;
  1648. case "movl pseudo-instruction":
  1649. instructionInfo = "Load a register with either a 32-bit or 64-bit immediate value or any address.";
  1650. break;
  1651. case "negs":
  1652. instructionInfo = "Negate, setting flags.";
  1653. break;
  1654. case "ngcs":
  1655. instructionInfo = "Negate with Carry, setting flags.";
  1656. break;
  1657. case "pacda":
  1658. instructionInfo = "Pointer Authentication Code for Data address, using key A.";
  1659. break;
  1660. case "pacdza":
  1661. instructionInfo = "Pointer Authentication Code for Data address, using key A.";
  1662. break;
  1663. case "pacdb":
  1664. instructionInfo = "Pointer Authentication Code for Data address, using key B.";
  1665. break;
  1666. case "pacdzb":
  1667. instructionInfo = "Pointer Authentication Code for Data address, using key B.";
  1668. break;
  1669. case "pacga":
  1670. instructionInfo = "Pointer Authentication Code, using Generic key.";
  1671. break;
  1672. case "pacia":
  1673. instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
  1674. break;
  1675. case "paciza":
  1676. instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
  1677. break;
  1678. case "pacia1716":
  1679. instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
  1680. break;
  1681. case "paciasp":
  1682. instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
  1683. break;
  1684. case "paciaz":
  1685. instructionInfo = "Pointer Authentication Code for Instruction address, using key A.";
  1686. break;
  1687. case "pacib":
  1688. instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
  1689. break;
  1690. case "pacizb":
  1691. instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
  1692. break;
  1693. case "pacib1716":
  1694. instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
  1695. break;
  1696. case "pacibsp":
  1697. instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
  1698. break;
  1699. case "pacibz":
  1700. instructionInfo = "Pointer Authentication Code for Instruction address, using key B.";
  1701. break;
  1702. case "psb":
  1703. instructionInfo = "Profiling Synchronization Barrier.";
  1704. break;
  1705. case "retaa":
  1706. instructionInfo = "Return from subroutine, with pointer authentication.";
  1707. break;
  1708. case "retab":
  1709. instructionInfo = "Return from subroutine, with pointer authentication.";
  1710. break;
  1711. case "rorv":
  1712. instructionInfo = "Rotate Right Variable.";
  1713. break;
  1714. case "sbcs":
  1715. instructionInfo = "Subtract with Carry, setting flags.";
  1716. break;
  1717. case "st2g":
  1718. instructionInfo = "Store Allocation Tags.";
  1719. break;
  1720. case "stg":
  1721. instructionInfo = "Store Allocation Tag.";
  1722. break;
  1723. case "stgp":
  1724. instructionInfo = "Store Allocation Tag and Pair of registers.";
  1725. break;
  1726. case "stgv":
  1727. instructionInfo = "Store Tag Vector.";
  1728. break;
  1729. case "stz2g":
  1730. instructionInfo = "Store Allocation Tags, Zeroing.";
  1731. break;
  1732. case "stzg":
  1733. instructionInfo = "Store Allocation Tag, Zeroing.";
  1734. break;
  1735. case "subg":
  1736. instructionInfo = "Subtract with Tag.";
  1737. break;
  1738. case "subp":
  1739. instructionInfo = "Subtract Pointer.";
  1740. break;
  1741. case "subps":
  1742. instructionInfo = "Subtract Pointer, setting Flags.";
  1743. break;
  1744. case "xaflag":
  1745. instructionInfo = "Convert floating-point condition flags from external format to Arm format.";
  1746. break;
  1747. case "xpacd":
  1748. instructionInfo = "Strip Pointer Authentication Code.";
  1749. break;
  1750. case "xpaci":
  1751. instructionInfo = "Strip Pointer Authentication Code.";
  1752. break;
  1753. case "xpaclri":
  1754. instructionInfo = "Strip Pointer Authentication Code.";
  1755. break;
  1756. case "casa":
  1757. instructionInfo = "Compare and Swap word or doubleword in memory.";
  1758. break;
  1759. case "casal":
  1760. instructionInfo = "Compare and Swap word or doubleword in memory.";
  1761. break;
  1762. case "cas":
  1763. instructionInfo = "Compare and Swap word or doubleword in memory.";
  1764. break;
  1765. case "casl":
  1766. instructionInfo = "Compare and Swap word or doubleword in memory.";
  1767. break;
  1768. case "casab":
  1769. instructionInfo = "Compare and Swap byte in memory.";
  1770. break;
  1771. case "casalb":
  1772. instructionInfo = "Compare and Swap byte in memory.";
  1773. break;
  1774. case "casb":
  1775. instructionInfo = "Compare and Swap byte in memory.";
  1776. break;
  1777. case "caslb":
  1778. instructionInfo = "Compare and Swap byte in memory.";
  1779. break;
  1780. case "casah":
  1781. instructionInfo = "Compare and Swap halfword in memory.";
  1782. break;
  1783. case "casalh":
  1784. instructionInfo = "Compare and Swap halfword in memory.";
  1785. break;
  1786. case "cash":
  1787. instructionInfo = "Compare and Swap halfword in memory.";
  1788. break;
  1789. case "caslh":
  1790. instructionInfo = "Compare and Swap halfword in memory.";
  1791. break;
  1792. case "caspa":
  1793. instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
  1794. break;
  1795. case "caspal":
  1796. instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
  1797. break;
  1798. case "casp":
  1799. instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
  1800. break;
  1801. case "caspl":
  1802. instructionInfo = "Compare and Swap Pair of words or doublewords in memory.";
  1803. break;
  1804. case "ldadda":
  1805. instructionInfo = "Atomic add on word or doubleword in memory.";
  1806. break;
  1807. case "ldaddal":
  1808. instructionInfo = "Atomic add on word or doubleword in memory.";
  1809. break;
  1810. case "ldadd":
  1811. instructionInfo = "Atomic add on word or doubleword in memory.";
  1812. break;
  1813. case "ldaddl":
  1814. instructionInfo = "Atomic add on word or doubleword in memory.";
  1815. break;
  1816. case "ldaddab":
  1817. instructionInfo = "Atomic add on byte in memory.";
  1818. break;
  1819. case "ldaddalb":
  1820. instructionInfo = "Atomic add on byte in memory.";
  1821. break;
  1822. case "ldaddb":
  1823. instructionInfo = "Atomic add on byte in memory.";
  1824. break;
  1825. case "ldaddlb":
  1826. instructionInfo = "Atomic add on byte in memory.";
  1827. break;
  1828. case "ldaddah":
  1829. instructionInfo = "Atomic add on halfword in memory.";
  1830. break;
  1831. case "ldaddalh":
  1832. instructionInfo = "Atomic add on halfword in memory.";
  1833. break;
  1834. case "ldaddh":
  1835. instructionInfo = "Atomic add on halfword in memory.";
  1836. break;
  1837. case "ldaddlh":
  1838. instructionInfo = "Atomic add on halfword in memory.";
  1839. break;
  1840. case "ldapr":
  1841. instructionInfo = "Load-Acquire RCpc Register.";
  1842. break;
  1843. case "ldaprb":
  1844. instructionInfo = "Load-Acquire RCpc Register Byte.";
  1845. break;
  1846. case "ldaprh":
  1847. instructionInfo = "Load-Acquire RCpc Register Halfword.";
  1848. break;
  1849. case "ldclra":
  1850. instructionInfo = "Atomic bit clear on word or doubleword in memory.";
  1851. break;
  1852. case "ldclral":
  1853. instructionInfo = "Atomic bit clear on word or doubleword in memory.";
  1854. break;
  1855. case "ldclr":
  1856. instructionInfo = "Atomic bit clear on word or doubleword in memory.";
  1857. break;
  1858. case "ldclrl":
  1859. instructionInfo = "Atomic bit clear on word or doubleword in memory.";
  1860. break;
  1861. case "ldclrab":
  1862. instructionInfo = "Atomic bit clear on byte in memory.";
  1863. break;
  1864. case "ldclralb":
  1865. instructionInfo = "Atomic bit clear on byte in memory.";
  1866. break;
  1867. case "ldclrb":
  1868. instructionInfo = "Atomic bit clear on byte in memory.";
  1869. break;
  1870. case "ldclrlb":
  1871. instructionInfo = "Atomic bit clear on byte in memory.";
  1872. break;
  1873. case "ldclrah":
  1874. instructionInfo = "Atomic bit clear on halfword in memory.";
  1875. break;
  1876. case "ldclralh":
  1877. instructionInfo = "Atomic bit clear on halfword in memory.";
  1878. break;
  1879. case "ldclrh":
  1880. instructionInfo = "Atomic bit clear on halfword in memory.";
  1881. break;
  1882. case "ldclrlh":
  1883. instructionInfo = "Atomic bit clear on halfword in memory.";
  1884. break;
  1885. case "ldeora":
  1886. instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
  1887. break;
  1888. case "ldeoral":
  1889. instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
  1890. break;
  1891. case "ldeor":
  1892. instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
  1893. break;
  1894. case "ldeorl":
  1895. instructionInfo = "Atomic exclusive OR on word or doubleword in memory.";
  1896. break;
  1897. case "ldeorab":
  1898. instructionInfo = "Atomic exclusive OR on byte in memory.";
  1899. break;
  1900. case "ldeoralb":
  1901. instructionInfo = "Atomic exclusive OR on byte in memory.";
  1902. break;
  1903. case "ldeorb":
  1904. instructionInfo = "Atomic exclusive OR on byte in memory.";
  1905. break;
  1906. case "ldeorlb":
  1907. instructionInfo = "Atomic exclusive OR on byte in memory.";
  1908. break;
  1909. case "ldeorah":
  1910. instructionInfo = "Atomic exclusive OR on halfword in memory.";
  1911. break;
  1912. case "ldeoralh":
  1913. instructionInfo = "Atomic exclusive OR on halfword in memory.";
  1914. break;
  1915. case "ldeorh":
  1916. instructionInfo = "Atomic exclusive OR on halfword in memory.";
  1917. break;
  1918. case "ldeorlh":
  1919. instructionInfo = "Atomic exclusive OR on halfword in memory.";
  1920. break;
  1921. case "ldlar":
  1922. instructionInfo = "Load LOAcquire Register.";
  1923. break;
  1924. case "ldlarb":
  1925. instructionInfo = "Load LOAcquire Register Byte.";
  1926. break;
  1927. case "ldlarh":
  1928. instructionInfo = "Load LOAcquire Register Halfword.";
  1929. break;
  1930. case "ldr pseudo-instruction":
  1931. instructionInfo = "Load a register with either a 32-bit or 64-bit immediate value or any address.";
  1932. break;
  1933. case "ldraa":
  1934. instructionInfo = "Load Register, with pointer authentication.";
  1935. break;
  1936. case "ldrab":
  1937. instructionInfo = "Load Register, with pointer authentication.";
  1938. break;
  1939. case "ldrex":
  1940. instructionInfo = "Load Register Exclusive.";
  1941. break;
  1942. case "strex":
  1943. instructionInfo = "Store Register Exclusive.";
  1944. break;
  1945. case "ldseta":
  1946. instructionInfo = "Atomic bit set on word or doubleword in memory.";
  1947. break;
  1948. case "ldsetal":
  1949. instructionInfo = "Atomic bit set on word or doubleword in memory.";
  1950. break;
  1951. case "ldset":
  1952. instructionInfo = "Atomic bit set on word or doubleword in memory.";
  1953. break;
  1954. case "ldsetl":
  1955. instructionInfo = "Atomic bit set on word or doubleword in memory.";
  1956. break;
  1957. case "ldsetab":
  1958. instructionInfo = "Atomic bit set on byte in memory.";
  1959. break;
  1960. case "ldsetalb":
  1961. instructionInfo = "Atomic bit set on byte in memory.";
  1962. break;
  1963. case "ldsetb":
  1964. instructionInfo = "Atomic bit set on byte in memory.";
  1965. break;
  1966. case "ldsetlb":
  1967. instructionInfo = "Atomic bit set on byte in memory.";
  1968. break;
  1969. case "ldsetah":
  1970. instructionInfo = "Atomic bit set on halfword in memory.";
  1971. break;
  1972. case "ldsetalh":
  1973. instructionInfo = "Atomic bit set on halfword in memory.";
  1974. break;
  1975. case "ldseth":
  1976. instructionInfo = "Atomic bit set on halfword in memory.";
  1977. break;
  1978. case "ldsetlh":
  1979. instructionInfo = "Atomic bit set on halfword in memory.";
  1980. break;
  1981. case "ldsmaxa":
  1982. instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
  1983. break;
  1984. case "ldsmaxal":
  1985. instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
  1986. break;
  1987. case "ldsmax":
  1988. instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
  1989. break;
  1990. case "ldsmaxl":
  1991. instructionInfo = "Atomic signed maximum on word or doubleword in memory.";
  1992. break;
  1993. case "ldsmaxab":
  1994. instructionInfo = "Atomic signed maximum on byte in memory.";
  1995. break;
  1996. case "ldsmaxalb":
  1997. instructionInfo = "Atomic signed maximum on byte in memory.";
  1998. break;
  1999. case "ldsmaxb":
  2000. instructionInfo = "Atomic signed maximum on byte in memory.";
  2001. break;
  2002. case "ldsmaxlb":
  2003. instructionInfo = "Atomic signed maximum on byte in memory.";
  2004. break;
  2005. case "ldsmaxah":
  2006. instructionInfo = "Atomic signed maximum on halfword in memory.";
  2007. break;
  2008. case "ldsmaxalh":
  2009. instructionInfo = "Atomic signed maximum on halfword in memory.";
  2010. break;
  2011. case "ldsmaxh":
  2012. instructionInfo = "Atomic signed maximum on halfword in memory.";
  2013. break;
  2014. case "ldsmaxlh":
  2015. instructionInfo = "Atomic signed maximum on halfword in memory.";
  2016. break;
  2017. case "ldsmina":
  2018. instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
  2019. break;
  2020. case "ldsminal":
  2021. instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
  2022. break;
  2023. case "ldsmin":
  2024. instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
  2025. break;
  2026. case "ldsminl":
  2027. instructionInfo = "Atomic signed minimum on word or doubleword in memory.";
  2028. break;
  2029. case "ldsminab":
  2030. instructionInfo = "Atomic signed minimum on byte in memory.";
  2031. break;
  2032. case "ldsminalb":
  2033. instructionInfo = "Atomic signed minimum on byte in memory.";
  2034. break;
  2035. case "ldsminb":
  2036. instructionInfo = "Atomic signed minimum on byte in memory.";
  2037. break;
  2038. case "ldsminlb":
  2039. instructionInfo = "Atomic signed minimum on byte in memory.";
  2040. break;
  2041. case "ldsminah":
  2042. instructionInfo = "Atomic signed minimum on halfword in memory.";
  2043. break;
  2044. case "ldsminalh":
  2045. instructionInfo = "Atomic signed minimum on halfword in memory.";
  2046. break;
  2047. case "ldsminh":
  2048. instructionInfo = "Atomic signed minimum on halfword in memory.";
  2049. break;
  2050. case "ldsminlh":
  2051. instructionInfo = "Atomic signed minimum on halfword in memory.";
  2052. break;
  2053. case "ldumaxa":
  2054. instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
  2055. break;
  2056. case "ldumaxal":
  2057. instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
  2058. break;
  2059. case "ldumax":
  2060. instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
  2061. break;
  2062. case "ldumaxl":
  2063. instructionInfo = "Atomic unsigned maximum on word or doubleword in memory.";
  2064. break;
  2065. case "ldumaxab":
  2066. instructionInfo = "Atomic unsigned maximum on byte in memory.";
  2067. break;
  2068. case "ldumaxalb":
  2069. instructionInfo = "Atomic unsigned maximum on byte in memory.";
  2070. break;
  2071. case "ldumaxb":
  2072. instructionInfo = "Atomic unsigned maximum on byte in memory.";
  2073. break;
  2074. case "ldumaxlb":
  2075. instructionInfo = "Atomic unsigned maximum on byte in memory.";
  2076. break;
  2077. case "ldumaxah":
  2078. instructionInfo = "Atomic unsigned maximum on halfword in memory.";
  2079. break;
  2080. case "ldumaxalh":
  2081. instructionInfo = "Atomic unsigned maximum on halfword in memory.";
  2082. break;
  2083. case "ldumaxh":
  2084. instructionInfo = "Atomic unsigned maximum on halfword in memory.";
  2085. break;
  2086. case "ldumaxlh":
  2087. instructionInfo = "Atomic unsigned maximum on halfword in memory.";
  2088. break;
  2089. case "ldumina":
  2090. instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
  2091. break;
  2092. case "lduminal":
  2093. instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
  2094. break;
  2095. case "ldumin":
  2096. instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
  2097. break;
  2098. case "lduminl":
  2099. instructionInfo = "Atomic unsigned minimum on word or doubleword in memory.";
  2100. break;
  2101. case "lduminab":
  2102. instructionInfo = "Atomic unsigned minimum on byte in memory.";
  2103. break;
  2104. case "lduminalb":
  2105. instructionInfo = "Atomic unsigned minimum on byte in memory.";
  2106. break;
  2107. case "lduminb":
  2108. instructionInfo = "Atomic unsigned minimum on byte in memory.";
  2109. break;
  2110. case "lduminlb":
  2111. instructionInfo = "Atomic unsigned minimum on byte in memory.";
  2112. break;
  2113. case "lduminah":
  2114. instructionInfo = "Atomic unsigned minimum on halfword in memory.";
  2115. break;
  2116. case "lduminalh":
  2117. instructionInfo = "Atomic unsigned minimum on halfword in memory.";
  2118. break;
  2119. case "lduminh":
  2120. instructionInfo = "Atomic unsigned minimum on halfword in memory.";
  2121. break;
  2122. case "lduminlh":
  2123. instructionInfo = "Atomic unsigned minimum on halfword in memory.";
  2124. break;
  2125. case "stadd":
  2126. instructionInfo = "Atomic add on word or doubleword in memory, without return.";
  2127. break;
  2128. case "staddl":
  2129. instructionInfo = "Atomic add on word or doubleword in memory, without return.";
  2130. break;
  2131. case "staddb":
  2132. instructionInfo = "Atomic add on byte in memory, without return.";
  2133. break;
  2134. case "staddlb":
  2135. instructionInfo = "Atomic add on byte in memory, without return.";
  2136. break;
  2137. case "staddh":
  2138. instructionInfo = "Atomic add on halfword in memory, without return.";
  2139. break;
  2140. case "staddlh":
  2141. instructionInfo = "Atomic add on halfword in memory, without return.";
  2142. break;
  2143. case "stclr":
  2144. instructionInfo = "Atomic bit clear on word or doubleword in memory, without return.";
  2145. break;
  2146. case "stclrl":
  2147. instructionInfo = "Atomic bit clear on word or doubleword in memory, without return.";
  2148. break;
  2149. case "stclrb":
  2150. instructionInfo = "Atomic bit clear on byte in memory, without return.";
  2151. break;
  2152. case "stclrlb":
  2153. instructionInfo = "Atomic bit clear on byte in memory, without return.";
  2154. break;
  2155. case "stclrh":
  2156. instructionInfo = "Atomic bit clear on halfword in memory, without return.";
  2157. break;
  2158. case "stclrlh":
  2159. instructionInfo = "Atomic bit clear on halfword in memory, without return.";
  2160. break;
  2161. case "steor":
  2162. instructionInfo = "Atomic exclusive OR on word or doubleword in memory, without return.";
  2163. break;
  2164. case "steorl":
  2165. instructionInfo = "Atomic exclusive OR on word or doubleword in memory, without return.";
  2166. break;
  2167. case "steorb":
  2168. instructionInfo = "Atomic exclusive OR on byte in memory, without return.";
  2169. break;
  2170. case "steorlb":
  2171. instructionInfo = "Atomic exclusive OR on byte in memory, without return.";
  2172. break;
  2173. case "steorh":
  2174. instructionInfo = "Atomic exclusive OR on halfword in memory, without return.";
  2175. break;
  2176. case "steorlh":
  2177. instructionInfo = "Atomic exclusive OR on halfword in memory, without return.";
  2178. break;
  2179. case "stllr":
  2180. instructionInfo = "Store LORelease Register.";
  2181. break;
  2182. case "stllrb":
  2183. instructionInfo = "Store LORelease Register Byte.";
  2184. break;
  2185. case "stllrh":
  2186. instructionInfo = "Store LORelease Register Halfword.";
  2187. break;
  2188. case "stset":
  2189. instructionInfo = "Atomic bit set on word or doubleword in memory, without return.";
  2190. break;
  2191. case "stsetl":
  2192. instructionInfo = "Atomic bit set on word or doubleword in memory, without return.";
  2193. break;
  2194. case "stsetb":
  2195. instructionInfo = "Atomic bit set on byte in memory, without return.";
  2196. break;
  2197. case "stsetlb":
  2198. instructionInfo = "Atomic bit set on byte in memory, without return.";
  2199. break;
  2200. case "stseth":
  2201. instructionInfo = "Atomic bit set on halfword in memory, without return.";
  2202. break;
  2203. case "stsetlh":
  2204. instructionInfo = "Atomic bit set on halfword in memory, without return.";
  2205. break;
  2206. case "stsmax":
  2207. instructionInfo = "Atomic signed maximum on word or doubleword in memory, without return.";
  2208. break;
  2209. case "stsmaxl":
  2210. instructionInfo = "Atomic signed maximum on word or doubleword in memory, without return.";
  2211. break;
  2212. case "stsmaxb":
  2213. instructionInfo = "Atomic signed maximum on byte in memory, without return.";
  2214. break;
  2215. case "stsmaxlb":
  2216. instructionInfo = "Atomic signed maximum on byte in memory, without return.";
  2217. break;
  2218. case "stsmaxh":
  2219. instructionInfo = "Atomic signed maximum on halfword in memory, without return.";
  2220. break;
  2221. case "stsmaxlh":
  2222. instructionInfo = "Atomic signed maximum on halfword in memory, without return.";
  2223. break;
  2224. case "stsmin":
  2225. instructionInfo = "Atomic signed minimum on word or doubleword in memory, without return.";
  2226. break;
  2227. case "stsminl":
  2228. instructionInfo = "Atomic signed minimum on word or doubleword in memory, without return.";
  2229. break;
  2230. case "stsminb":
  2231. instructionInfo = "Atomic signed minimum on byte in memory, without return.";
  2232. break;
  2233. case "stsminlb":
  2234. instructionInfo = "Atomic signed minimum on byte in memory, without return.";
  2235. break;
  2236. case "stsminh":
  2237. instructionInfo = "Atomic signed minimum on halfword in memory, without return.";
  2238. break;
  2239. case "stsminlh":
  2240. instructionInfo = "Atomic signed minimum on halfword in memory, without return.";
  2241. break;
  2242. case "stumax":
  2243. instructionInfo = "Atomic unsigned maximum on word or doubleword in memory, without return.";
  2244. break;
  2245. case "stumaxl":
  2246. instructionInfo = "Atomic unsigned maximum on word or doubleword in memory, without return.";
  2247. break;
  2248. case "stumaxb":
  2249. instructionInfo = "Atomic unsigned maximum on byte in memory, without return.";
  2250. break;
  2251. case "stumaxlb":
  2252. instructionInfo = "Atomic unsigned maximum on byte in memory, without return.";
  2253. break;
  2254. case "stumaxh":
  2255. instructionInfo = "Atomic unsigned maximum on halfword in memory, without return.";
  2256. break;
  2257. case "stumaxlh":
  2258. instructionInfo = "Atomic unsigned maximum on halfword in memory, without return.";
  2259. break;
  2260. case "stumin":
  2261. instructionInfo = "Atomic unsigned minimum on word or doubleword in memory, without return.";
  2262. break;
  2263. case "stuminl":
  2264. instructionInfo = "Atomic unsigned minimum on word or doubleword in memory, without return.";
  2265. break;
  2266. case "stuminb":
  2267. instructionInfo = "Atomic unsigned minimum on byte in memory, without return.";
  2268. break;
  2269. case "stuminlb":
  2270. instructionInfo = "Atomic unsigned minimum on byte in memory, without return.";
  2271. break;
  2272. case "stuminh":
  2273. instructionInfo = "Atomic unsigned minimum on halfword in memory, without return.";
  2274. break;
  2275. case "stuminlh":
  2276. instructionInfo = "Atomic unsigned minimum on halfword in memory, without return.";
  2277. break;
  2278. case "swpa":
  2279. instructionInfo = "Swap word or doubleword in memory.";
  2280. break;
  2281. case "swpal":
  2282. instructionInfo = "Swap word or doubleword in memory.";
  2283. break;
  2284. case "swp":
  2285. instructionInfo = "Swap word or doubleword in memory.";
  2286. break;
  2287. case "swpl":
  2288. instructionInfo = "Swap word or doubleword in memory.";
  2289. break;
  2290. case "swpab":
  2291. instructionInfo = "Swap byte in memory.";
  2292. break;
  2293. case "swpalb":
  2294. instructionInfo = "Swap byte in memory.";
  2295. break;
  2296. case "swpb":
  2297. instructionInfo = "Swap byte in memory.";
  2298. break;
  2299. case "swplb":
  2300. instructionInfo = "Swap byte in memory.";
  2301. break;
  2302. case "swpah":
  2303. instructionInfo = "Swap halfword in memory.";
  2304. break;
  2305. case "swpalh":
  2306. instructionInfo = "Swap halfword in memory.";
  2307. break;
  2308. case "swph":
  2309. instructionInfo = "Swap halfword in memory.";
  2310. break;
  2311. case "swplh":
  2312. instructionInfo = "Swap halfword in memory.";
  2313. break;
  2314. case "fjcvtzs":
  2315. instructionInfo = "Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero.";
  2316. break;
  2317. case "fcmla":
  2318. instructionInfo = "Floating-point Complex Multiply Accumulate (by element).";
  2319. break;
  2320. case "fmlal":
  2321. instructionInfo = "Floating-point fused Multiply-Add Long to accumulator (by element).";
  2322. break;
  2323. case "":
  2324. instructionInfo = "Floating-point fused Multiply-Add Long to accumulator (by element).";
  2325. break;
  2326. case "fmlsl":
  2327. instructionInfo = "Floating-point fused Multiply-Subtract Long from accumulator (by element).";
  2328. break;
  2329. case "sqrdmlah":
  2330. instructionInfo = "Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element).";
  2331. break;
  2332. case "sqrdmlsh":
  2333. instructionInfo = "Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element).";
  2334. break;
  2335. case "fcadd":
  2336. instructionInfo = "Floating-point Complex Add.";
  2337. break;
  2338. case "sdot":
  2339. instructionInfo = "Dot Product signed arithmetic (vector, by element).";
  2340. break;
  2341. case "sxtl":
  2342. instructionInfo = "Signed extend Long.";
  2343. break;
  2344. case "sxtl2":
  2345. instructionInfo = "Signed extend Long.";
  2346. break;
  2347. case "udot":
  2348. instructionInfo = "Dot Product unsigned arithmetic (vector, by element).";
  2349. break;
  2350. case "uxtl":
  2351. instructionInfo = "Unsigned extend Long.";
  2352. break;
  2353. case "uxtl2":
  2354. instructionInfo = "Unsigned extend Long.";
  2355. break;
  2356. case "bcax":
  2357. instructionInfo = "SHA3 Bit Clear and XOR.";
  2358. break;
  2359. case "eor3":
  2360. instructionInfo = "SHA3 Three-way Exclusive OR.";
  2361. break;
  2362. case "rax1":
  2363. instructionInfo = "SHA3 Rotate and Exclusive OR.";
  2364. break;
  2365. case "sha512h2":
  2366. instructionInfo = "SHA512 Hash update part 2.";
  2367. break;
  2368. case "sha512h":
  2369. instructionInfo = "SHA512 Hash update part 1.";
  2370. break;
  2371. case "sha512su0":
  2372. instructionInfo = "SHA512 Schedule Update 0.";
  2373. break;
  2374. case "sha512su1":
  2375. instructionInfo = "SHA512 Schedule Update 1.";
  2376. break;
  2377. case "sm3partw1":
  2378. instructionInfo = "SM3 three-way exclusive OR on the combination of three 128-bit vectors.";
  2379. break;
  2380. case "sm3partw2":
  2381. instructionInfo = "SM3 three-way exclusive OR on the combination of three 128-bit vectors.";
  2382. break;
  2383. case "sm3ss1":
  2384. instructionInfo = "SM3 perform rotates and adds on three 128-bit vectors combined into a destination 128-bit SIMD and FP register.";
  2385. break;
  2386. case "sm3tt1a":
  2387. instructionInfo = "SM3 three-way exclusive OR on the combination of three 128-bit vectors and a 2-bit immediate index value.";
  2388. break;
  2389. case "sm3tt1b":
  2390. instructionInfo = "SM3 perform 32-bit majority function on the combination of three 128-bit vectors and 2-bit immediate index value.";
  2391. break;
  2392. case "sm3tt2a":
  2393. instructionInfo = "SM3 three-way exclusive OR of combined three 128-bit vectors and a 2-bit immediate index value.";
  2394. break;
  2395. case "sm3tt2b":
  2396. instructionInfo = "SM3 perform 32-bit majority function on the combination of three 128-bit vectors and 2-bit immediate index value.";
  2397. break;
  2398. case "sm4e":
  2399. instructionInfo = "SM4 Encode.";
  2400. break;
  2401. case "sm4ekey":
  2402. instructionInfo = "SM4 Key.";
  2403. break;
  2404. case "xar":
  2405. instructionInfo = "SHA3 Exclusive OR and Rotate.";
  2406. break;
  2407. case "vaba":
  2408. instructionInfo = "Absolute difference and Accumulate, Absolute difference and Accumulate Long.";
  2409. break;
  2410. case "vabl":
  2411. instructionInfo = "Absolute difference and Accumulate, Absolute difference and Accumulate Long.";
  2412. break;
  2413. case "vabd":
  2414. instructionInfo = "Absolute difference, Absolute difference Long.";
  2415. break;
  2416. case "vabdl":
  2417. instructionInfo = "Absolute difference, Absolute difference Long.";
  2418. break;
  2419. case "vacge":
  2420. instructionInfo = "Absolute Compare Greater than or Equal, Greater Than.";
  2421. break;
  2422. case "vacgt":
  2423. instructionInfo = "Absolute Compare Greater than or Equal, Greater Than.";
  2424. break;
  2425. case "vacle":
  2426. instructionInfo = "Absolute Compare Less than or Equal, Less Than (pseudo-instructions).";
  2427. break;
  2428. case "vaclt":
  2429. instructionInfo = "Absolute Compare Less than or Equal, Less Than (pseudo-instructions).";
  2430. break;
  2431. case "vaddhn":
  2432. instructionInfo = "Add, select High half.";
  2433. break;
  2434. case "vand":
  2435. instructionInfo = "Bitwise AND.";
  2436. break;
  2437. case "vbic":
  2438. instructionInfo = "Bitwise Bit Clear (register).";
  2439. break;
  2440. case "vbif":
  2441. instructionInfo = "Bitwise Insert if False.";
  2442. break;
  2443. case "vbit":
  2444. instructionInfo = "Bitwise Insert if True.";
  2445. break;
  2446. case "vbsl":
  2447. instructionInfo = "Bitwise Select.";
  2448. break;
  2449. case "vceq":
  2450. instructionInfo = "Compare Equal.";
  2451. break;
  2452. case "vcge":
  2453. instructionInfo = "Compare Greater than or Equal.";
  2454. break;
  2455. case "vcgt":
  2456. instructionInfo = "Compare Greater Than.";
  2457. break;
  2458. case "vcle":
  2459. instructionInfo = "Compare Less than or Equal.";
  2460. break;
  2461. case "vcls":
  2462. instructionInfo = "Count Leading Sign bits.";
  2463. break;
  2464. case "vcnt":
  2465. instructionInfo = "Count set bits.";
  2466. break;
  2467. case "vclt":
  2468. instructionInfo = "Compare Less Than.";
  2469. break;
  2470. case "vclz":
  2471. instructionInfo = "Count Leading Zeros.";
  2472. break;
  2473. case "vcvt":
  2474. instructionInfo = "Convert fixed-point or integer to floating point, floating-point to integer or fixed-point.";
  2475. break;
  2476. case "vdup":
  2477. instructionInfo = "Duplicate scalar to all lanes of vector.";
  2478. break;
  2479. case "veor":
  2480. instructionInfo = "Bitwise Exclusive OR.";
  2481. break;
  2482. case "vext":
  2483. instructionInfo = "Extract.";
  2484. break;
  2485. case "vfma":
  2486. instructionInfo = "Fused Multiply Accumulate, Fused Multiply Subtract (vector).";
  2487. break;
  2488. case "vfms":
  2489. instructionInfo = "Fused Multiply Accumulate, Fused Multiply Subtract (vector).";
  2490. break;
  2491. case "vhadd":
  2492. instructionInfo = "Halving Add.";
  2493. break;
  2494. case "vhsub":
  2495. instructionInfo = "Halving Subtract.";
  2496. break;
  2497. case "vld":
  2498. case "vld1":
  2499. case "vld2":
  2500. case "vld3":
  2501. case "vld4":
  2502. instructionInfo = "Vector Load.";
  2503. break;
  2504. case "vmax":
  2505. instructionInfo = "Maximum, Minimum.";
  2506. break;
  2507. case "vmin":
  2508. instructionInfo = "Maximum, Minimum.";
  2509. break;
  2510. case "vmla":
  2511. instructionInfo = "Multiply Accumulate (vector).";
  2512. break;
  2513. case "vmls":
  2514. instructionInfo = "Multiply Subtract (vector).";
  2515. break;
  2516. case "vmovl":
  2517. instructionInfo = "Move Long (register).";
  2518. break;
  2519. case "vmovn":
  2520. instructionInfo = "Move Narrow (register).";
  2521. break;
  2522. case "vmvn":
  2523. instructionInfo = "Move Negative (immediate).";
  2524. break;
  2525. case "vneg":
  2526. instructionInfo = "Negate.";
  2527. break;
  2528. case "vorn":
  2529. instructionInfo = "Bitwise OR NOT.";
  2530. break;
  2531. case "vorr":
  2532. instructionInfo = "Bitwise OR (register).";
  2533. break;
  2534. case "vpadal":
  2535. instructionInfo = "Pairwise Add and Accumulate Long.";
  2536. break;
  2537. case "vpadd":
  2538. instructionInfo = "Pairwise Add.";
  2539. break;
  2540. case "vpmax":
  2541. instructionInfo = "Pairwise Maximum, Pairwise Minimum.";
  2542. break;
  2543. case "vpmin":
  2544. instructionInfo = "Pairwise Maximum, Pairwise Minimum.";
  2545. break;
  2546. case "vqabs":
  2547. instructionInfo = "Absolute value, saturate.";
  2548. break;
  2549. case "vqadd":
  2550. instructionInfo = "Add, saturate.";
  2551. break;
  2552. case "vqdmlal":
  2553. instructionInfo = "Saturating Doubling Multiply Accumulate, and Multiply Subtract.";
  2554. break;
  2555. case "vqdmlsl":
  2556. instructionInfo = "Saturating Doubling Multiply Accumulate, and Multiply Subtract.";
  2557. break;
  2558. case "vqdmull":
  2559. instructionInfo = "Saturating Doubling Multiply.";
  2560. break;
  2561. case "vqdmulh":
  2562. instructionInfo = "Saturating Doubling Multiply returning High half.";
  2563. break;
  2564. case "vqmovn":
  2565. instructionInfo = "Saturating Move (register).";
  2566. break;
  2567. case "vqneg":
  2568. instructionInfo = "Negate, saturate.";
  2569. break;
  2570. case "vqrdmulh":
  2571. instructionInfo = "Saturating Doubling Multiply returning High half.";
  2572. break;
  2573. case "vqrshl":
  2574. instructionInfo = "Shift Left, Round, saturate (by signed variable).";
  2575. break;
  2576. case "vqrshrn":
  2577. instructionInfo = "Shift Right, Round, saturate (by immediate).";
  2578. break;
  2579. case "vqshl":
  2580. instructionInfo = "Shift Left, saturate (by immediate).";
  2581. break;
  2582. case "vqshrn":
  2583. instructionInfo = "Shift Right, saturate (by immediate).";
  2584. break;
  2585. case "vqsub":
  2586. instructionInfo = "Subtract, saturate.";
  2587. break;
  2588. case "vraddhn":
  2589. instructionInfo = "Add, select High half, Round.";
  2590. break;
  2591. case "vrecpe":
  2592. instructionInfo = "Reciprocal Estimate.";
  2593. break;
  2594. case "vrecps":
  2595. instructionInfo = "Reciprocal Step.";
  2596. break;
  2597. case "vrev":
  2598. case "vrev16":
  2599. case "vrev32":
  2600. case "vrev64":
  2601. instructionInfo = "Reverse elements.";
  2602. break;
  2603. case "vrhadd":
  2604. instructionInfo = "Halving Add, Round.";
  2605. break;
  2606. case "vrshr":
  2607. instructionInfo = "Shift Right and Round (by immediate).";
  2608. break;
  2609. case "vrshrn":
  2610. instructionInfo = "Shift Right, Round, Narrow (by immediate).";
  2611. break;
  2612. case "vrsqrte":
  2613. instructionInfo = "Reciprocal Square Root Estimate.";
  2614. break;
  2615. case "vrsqrts":
  2616. instructionInfo = "Reciprocal Square Root Step.";
  2617. break;
  2618. case "vrsra":
  2619. instructionInfo = "Shift Right, Round, and Accumulate (by immediate).";
  2620. break;
  2621. case "vrsubhn":
  2622. instructionInfo = "Subtract, select High half, Round.";
  2623. break;
  2624. case "vshl":
  2625. instructionInfo = "Shift Left (by immediate).";
  2626. break;
  2627. case "vshr":
  2628. instructionInfo = "Shift Right (by immediate).";
  2629. break;
  2630. case "vshrn":
  2631. instructionInfo = "Shift Right, Narrow (by immediate).";
  2632. break;
  2633. case "vsli":
  2634. instructionInfo = "Shift Left and Insert.";
  2635. break;
  2636. case "vsra":
  2637. instructionInfo = "Shift Right, Accumulate (by immediate).";
  2638. break;
  2639. case "vsri":
  2640. instructionInfo = "Shift Right and Insert.";
  2641. break;
  2642. case "vst":
  2643. case "vst1":
  2644. case "vst2":
  2645. case "vst3":
  2646. case "vst4":
  2647. instructionInfo = "Vector Store.";
  2648. break;
  2649. case "vsubhn":
  2650. instructionInfo = "Subtract, select High half.";
  2651. break;
  2652. case "vswp":
  2653. instructionInfo = "Swap vectors.";
  2654. break;
  2655. case "vtbl":
  2656. instructionInfo = "Vector table look-up.";
  2657. break;
  2658. case "vtbx":
  2659. instructionInfo = "Vector table look-up.";
  2660. break;
  2661. case "vtrn":
  2662. instructionInfo = "Vector transpose.";
  2663. break;
  2664. case "vtst":
  2665. instructionInfo = "Test bits.";
  2666. break;
  2667. case "vuzp":
  2668. instructionInfo = "Vector de-interleave.";
  2669. break;
  2670. case "vzip":
  2671. instructionInfo = "Vector interleave.";
  2672. break;
  2673. case "vldm":
  2674. case "vldmia":
  2675. case "vldmdb":
  2676. instructionInfo = "Load multiple.";
  2677. break;
  2678. case "vldr":
  2679. instructionInfo = "Load (see also VLDR pseudo-instruction).";
  2680. break;
  2681. case "vmrs":
  2682. instructionInfo = "Transfer from NEON and VFP system register to ARM register.";
  2683. break;
  2684. case "vmsr":
  2685. instructionInfo = "Transfer from ARM register to NEON and VFP system register.";
  2686. break;
  2687. case "vpop":
  2688. instructionInfo = "Pop VFP or NEON registers from full-descending stack.";
  2689. break;
  2690. case "vpush":
  2691. instructionInfo = "Push VFP or NEON registers to full-descending stack.";
  2692. break;
  2693. case "vstm":
  2694. case "vstmia":
  2695. instructionInfo = "Store multiple.";
  2696. break;
  2697. case "vstr":
  2698. instructionInfo = "Store.";
  2699. break;
  2700. case "vcmp":
  2701. instructionInfo = "Compare.";
  2702. break;
  2703. case "vcmpe":
  2704. instructionInfo = "Compare.";
  2705. break;
  2706. case "vcvtb":
  2707. instructionInfo = "Convert between half-precision and single-precision floating-point.";
  2708. break;
  2709. case "vcvtt":
  2710. instructionInfo = "Convert between half-precision and single-precision floating-point.";
  2711. break;
  2712. case "vdiv":
  2713. instructionInfo = "Divide.";
  2714. break;
  2715. case "vfnma":
  2716. instructionInfo = "Fused multiply accumulate with negation, Fused multiply subtract with negation.";
  2717. break;
  2718. case "vfnms":
  2719. instructionInfo = "Fused multiply accumulate with negation, Fused multiply subtract with negation.";
  2720. break;
  2721. case "vnmla":
  2722. instructionInfo = "Negated multiply accumulate.";
  2723. break;
  2724. case "vnmls":
  2725. instructionInfo = "Negated multiply subtract.";
  2726. break;
  2727. case "vnmul":
  2728. instructionInfo = "Negated multiply.";
  2729. break;
  2730. case "vsqrt":
  2731. instructionInfo = "Square Root.";
  2732. break;
  2733. case "push":
  2734. instructionInfo = "Push registers onto a full descending stack.";
  2735. break;
  2736. case "pop":
  2737. instructionInfo = "Pop registers of a full descending stack.";
  2738. break;
  2739. case "pkhbt":
  2740. case "pkhtb":
  2741. instructionInfo = "Halfword Packing instructions. Combine a halfword from one register with a halfword from another register.";
  2742. break;
  2743. default:
  2744. instructionInfo = string.Empty;
  2745. returnValue = false;
  2746. break;
  2747. }
  2748. return returnValue;
  2749. }
  2750. }
  2751. }
  2752. }